The present invention relates generally to digital systems and more particularly to increasing the processing speeds of the digital systems.
Most digital systems are organized into a number of processing stages, known as pipeline stages, to increase their throughput. An N-stage pipelined system may require N cycles to produce one result but it can also produce N number of results in that same N number of cycles. Since pipelined systems must operate at the speed of the slowest pipeline stage, much effort is spent in increasing the processing speed of the slowest pipeline stage.
Accordingly, what is needed is a system and method for increasing the overall processing speed of digital systems. The present invention addresses such a need.
A self-adjusting multi-speed pipeline in accordance with the present invention is disclosed. A self-adjusting multi-speed pipeline is aware of the required processing time of the slowest among the stages that are actually used in each cycle and to adjust the clock speed accordingly. Intelligence is added to the pipeline to detect when one or more of slower pipeline stages are to be used in each cycle. A clock generator observes these detection signals and increases or decreases the clock period in each cycle to ensure that the slowest pipeline stage completes its processing.
The biggest benefit of such a pipeline is improved performance since the pipeline can now operate more efficiently. The speed of the pipeline is reduced only enough for the slowest stage in each cycle to complete its processing. Another benefit is that less effort can be spent in reducing the required processing time of slower pipeline stages, resulting in simpler and smaller systems and shorter design time without sacrificing the overall performance.